Emil J 13795203a1 Merge pull request #5680 from YosysHQ/emi/aiger-add-bounds-checks ...

aigerparse: add some bounds checks

2026-02-20 11:53:49 +01:00

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aiger

aigerparse: sanity-check AIGER header

2026-02-11 11:46:17 +00:00

aiger2

Enable xaiger2 pass when not in NDEBUG

2025-11-21 14:23:32 -08:00

ast

verilog: Do not set module_not_derived on internal cells

2026-01-19 16:48:13 -08:00

blif

blifparse: add bounds check

2026-02-11 12:16:02 +01:00

json

Support param. default values in JSON FE and SV BE

2026-02-11 08:10:55 -08:00

liberty

read_liberty: support loopy retention cells

2025-11-20 13:21:32 +01:00

rpc

Remove .c_str() from parameters to log_debug()

2025-09-23 19:10:33 +12:00

rtlil

Add -legalize option to read_rtlil

2025-12-21 21:47:48 +00:00

verific

Guard vhdl_file::UNDEFINED behind VERIFIC_VHDL_SUPPORT.

2026-02-02 15:26:03 -08:00

verilog

read_verilog: remove log I left behind by accident

2026-01-13 18:47:23 +01:00