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mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-07 04:19:56 +02:00
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7e2fc2eaeb70179c8da3e5dc8be800f486d5b912
yosys/frontends/verilog
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Lukasz Dalek 83ddc62034 Rewrite multirange arrays sizes [n] as [n-1:0]
Signed-off-by: Lukasz Dalek <[email protected]>
2020-08-03 14:48:27 +02:00
..
.gitignore
Add "make coverage"
2018-08-27 14:22:21 +02:00
const2ast.cc
Replacing log_error for log_file_error due consistency
2020-03-31 12:01:29 -06:00
Makefile.inc
Treat all bison warnings as errors in verilog front-end
2020-07-15 11:57:31 +02:00
preproc.cc
MSVC does not understand __builtin_unreachable
2020-06-17 15:10:08 +02:00
preproc.h
Add support for SystemVerilog-style `define to Verilog frontend
2020-03-27 16:08:26 +00:00
verilog_frontend.cc
Use C++11 final/override keywords.
2020-06-18 23:34:52 +00:00
verilog_frontend.h
frontend: cleanup to use more ID::*, more dict<> instead of map<>
2020-05-04 10:48:37 -07:00
verilog_lexer.l
Merge pull request #2179 from splhack/static-cast
2020-07-01 16:40:20 +02:00
verilog_parser.y
Rewrite multirange arrays sizes [n] as [n-1:0]
2020-08-03 14:48:27 +02:00
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