mirror of https://github.com/YosysHQ/yosys.git
363 lines
5.9 KiB
Plaintext
363 lines
5.9 KiB
Plaintext
log -header "Simple positive case with AND"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire s1,
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input wire s2,
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input wire a,
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input wire b,
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input wire c,
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input wire d,
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output wire x
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);
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wire m1, m2;
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assign m1 = s1 ? b : a;
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assign m2 = m1 & c;
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assign x = s2 ? m2 : d;
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endmodule
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EOF
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check -assert
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# # Show pre
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# autoname
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# write_json pre.json
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# exec -- netlistsvg pre.json -o pre.svg
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# Check equivalence after muxmode
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equiv_opt -assert muxmode
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# Check final design has correct number of gates
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design -load postopt
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select -assert-count 3 t:$mux
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# # Show post
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# autoname
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# write_json post.json
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# exec -- netlistsvg post.json -o post.svg
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design -reset
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log -pop
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log -header "Simple positive case with AND (order reversed)"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire s1,
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input wire s2,
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input wire a,
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input wire b,
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input wire c,
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input wire d,
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output wire x
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);
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wire m1, m2;
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assign m1 = s1 ? b : a;
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assign m2 = c & m1;
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assign x = s2 ? m2 : d;
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endmodule
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EOF
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check -assert
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# # Show pre
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# autoname
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# write_json pre.json
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# exec -- netlistsvg pre.json -o pre.svg
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# Check equivalence after muxmode
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equiv_opt -assert muxmode
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# Check final design has correct number of gates
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design -load postopt
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select -assert-count 3 t:$mux
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# # Show post
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# autoname
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# write_json post.json
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# exec -- netlistsvg post.json -o post.svg
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design -reset
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log -pop
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log -header "Simple positive case with OR"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire s1,
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input wire s2,
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input wire a,
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input wire b,
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input wire c,
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input wire d,
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output wire x
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);
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wire m1, m2;
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assign m1 = s1 ? b : a;
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assign m2 = m1 | c;
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assign x = s2 ? m2 : d;
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endmodule
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EOF
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check -assert
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# # Show pre
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# autoname
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# write_json pre.json
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# exec -- netlistsvg pre.json -o pre.svg
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# Check equivalence after muxmode
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equiv_opt -assert muxmode
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# Check final design has correct number of gates
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design -load postopt
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select -assert-count 3 t:$mux
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# # Show post
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# autoname
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# write_json post.json
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# exec -- netlistsvg post.json -o post.svg
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design -reset
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log -pop
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log -header "Simple positive case with OR (order reversed)"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire s1,
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input wire s2,
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input wire a,
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input wire b,
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input wire c,
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input wire d,
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output wire x
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);
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wire m1, m2;
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assign m1 = s1 ? b : a;
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assign m2 = c | m1;
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assign x = s2 ? m2 : d;
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endmodule
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EOF
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check -assert
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# # Show pre
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# autoname
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# write_json pre.json
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# exec -- netlistsvg pre.json -o pre.svg
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# Check equivalence after muxmode
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equiv_opt -assert muxmode
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# Check final design has correct number of gates
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design -load postopt
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select -assert-count 3 t:$mux
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# # Show post
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# autoname
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# write_json post.json
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# exec -- netlistsvg post.json -o post.svg
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design -reset
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log -pop
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log -header "Simple negative case with multi-bit AND"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire [1:0] s1,
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input wire [1:0] s2,
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input wire [1:0] a,
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input wire [1:0] b,
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input wire [1:0] c,
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input wire [1:0] d,
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output wire [1:0] x
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);
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wire m1, m2;
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assign m1 = s1 ? b : a;
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assign m2 = m1 & c;
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assign x = s2 ? m2 : d;
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endmodule
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EOF
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check -assert
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# # Show pre
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# autoname
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# write_json pre.json
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# exec -- netlistsvg pre.json -o pre.svg
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# Check equivalence after muxmode
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equiv_opt -assert muxmode
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# Check final design has correct number of gates
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design -load postopt
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select -assert-count 1 t:$and
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select -assert-count 2 t:$mux
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# # Show post
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# autoname
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# write_json post.json
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# exec -- netlistsvg post.json -o post.svg
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design -reset
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log -pop
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log -header "Simple negative case with multi-bit AND (order reversed)"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire [1:0] s1,
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input wire [1:0] s2,
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input wire [1:0] a,
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input wire [1:0] b,
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input wire [1:0] c,
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input wire [1:0] d,
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output wire [1:0] x
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);
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wire m1, m2;
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assign m1 = s1 ? b : a;
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assign m2 = c & m1;
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assign x = s2 ? m2 : d;
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endmodule
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EOF
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check -assert
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# # Show pre
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# autoname
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# write_json pre.json
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# exec -- netlistsvg pre.json -o pre.svg
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# Check equivalence after muxmode
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equiv_opt -assert muxmode
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# Check final design has correct number of gates
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design -load postopt
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select -assert-count 1 t:$and
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select -assert-count 2 t:$mux
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# # Show post
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# autoname
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# write_json post.json
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# exec -- netlistsvg post.json -o post.svg
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design -reset
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log -pop
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log -header "Simple negative case with OR"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire [1:0] s1,
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input wire [1:0] s2,
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input wire [1:0] a,
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input wire [1:0] b,
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input wire [1:0] c,
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input wire [1:0] d,
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output wire [1:0] x
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);
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wire m1, m2;
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assign m1 = s1 ? b : a;
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assign m2 = m1 | c;
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assign x = s2 ? m2 : d;
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endmodule
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EOF
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check -assert
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# # Show pre
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# autoname
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# write_json pre.json
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# exec -- netlistsvg pre.json -o pre.svg
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# Check equivalence after muxmode
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equiv_opt -assert muxmode
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# Check final design has correct number of gates
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design -load postopt
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select -assert-count 1 t:$or
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select -assert-count 2 t:$mux
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# # Show post
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# autoname
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# write_json post.json
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# exec -- netlistsvg post.json -o post.svg
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design -reset
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log -pop
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log -header "Simple negative case with multi-bit OR (order reversed)"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire [1:0] s1,
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input wire [1:0] s2,
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input wire [1:0] a,
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input wire [1:0] b,
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input wire [1:0] c,
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input wire [1:0] d,
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output wire [1:0] x
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);
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wire m1, m2;
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assign m1 = s1 ? b : a;
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assign m2 = c | m1;
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assign x = s2 ? m2 : d;
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endmodule
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EOF
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check -assert
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# # Show pre
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# autoname
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# write_json pre.json
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# exec -- netlistsvg pre.json -o pre.svg
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# Check equivalence after muxmode
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equiv_opt -assert muxmode
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# Check final design has correct number of gates
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design -load postopt
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select -assert-count 1 t:$or
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select -assert-count 2 t:$mux
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# # Show post
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# autoname
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# write_json post.json
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# exec -- netlistsvg post.json -o post.svg
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design -reset
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log -pop
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