Clifford Wolf 397b00252d Added $shift and $shiftx cell types (needed for correct part select behavior)

2014-07-29 16:35:13 +02:00

..

ast.cc

Added support for "upto" wires to Verilog front- and back-end

2014-07-28 14:25:03 +02:00

ast.h

Added support for "upto" wires to Verilog front- and back-end

2014-07-28 14:25:03 +02:00

genrtlil.cc

Added $shift and $shiftx cell types (needed for correct part select behavior)

2014-07-29 16:35:13 +02:00

Makefile.inc

initial import

2013-01-05 11:13:26 +01:00

simplify.cc

Removed left over debug code

2014-07-28 19:38:30 +02:00