Clifford Wolf e6df25bf74 Renamed "write_autotest" to "test_autotb" and moved to passes/tests/

2014-07-29 21:12:50 +02:00

..

blif

Using log_assert() instead of assert()

2014-07-28 11:27:48 +02:00

btor

Added $shift and $shiftx cell types (needed for correct part select behavior)

2014-07-29 16:35:13 +02:00

edif

Using log_assert() instead of assert()

2014-07-28 11:27:48 +02:00

ilang

Added wire->upto flag for signals such as "wire [0:7] x;"

2014-07-28 12:12:13 +02:00

intersynth

Using log_assert() instead of assert()

2014-07-28 11:27:48 +02:00

spice

Using log_assert() instead of assert()

2014-07-28 11:27:48 +02:00

verilog

Added support for "upto" wires to Verilog front- and back-end

2014-07-28 14:25:03 +02:00