Logo
Explore Help
Sign In
luke/yosys
Watch 1
Star 0
Fork 0
mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-02 22:58:32 +02:00
Code Issues Packages Projects Releases Wiki Activity
Files
7c57d8fbb44cdc466f4e384528109ada7e52b4c1
yosys/techlibs
T
History
Larry Doolittle 50bcd9a728 Clean whitespace and permissions in techlibs/intel
2017-10-05 16:23:49 +02:00
..
achronix
Adding Cyclone IV (E, GX), Arria 10, Cyclone V and LPM functions (ALTPLL and M9K); M9K is not finished yet. Achronix Speedster also in this commit. Both Arria10 and Speedster-i are still experimental due complexity, but you can experiment around those devices right now
2017-10-01 11:04:17 -05:00
common
Add dff2ff.v techmap file
2017-05-31 11:45:58 +02:00
coolrunner2
coolrunner2: Finish fixing special-use p-terms
2017-09-01 07:22:16 -07:00
easic
Add first draft of eASIC back-end
2017-09-29 17:53:43 +02:00
gowin
Indenting fixes in gowin sim cell lib
2016-11-08 18:54:00 +01:00
greenpak4
Added RESET_TO_MAX parameter to $__COUNT_ cell. Cannot yet be extracted.
2017-09-14 10:26:32 -07:00
ice40
Fix synth_ice40 doc regarding -top default
2017-09-29 17:52:57 +02:00
intel
Clean whitespace and permissions in techlibs/intel
2017-10-05 16:23:49 +02:00
xilinx
Add techlibs/xilinx/lut2lut.v
2017-07-10 12:09:05 +02:00
.gitignore
added .gitignore files
2013-01-05 11:19:11 +01:00
Powered by Gitea Version: 1.27.2 Page: 2444ms Template: 87ms
Auto
English
Bahasa Indonesia Deutsch English Español Français Gaeilge Italiano Latviešu Magyar nyelv Nederlands Polski Português de Portugal Português do Brasil Suomi Svenska Türkçe Čeština Ελληνικά Български Русский Українська فارسی മലയാളം 日本語 简体中文 繁體中文(台灣) 繁體中文(香港) 한국어
Licenses API