Clifford Wolf 7bf4e4a185 Improve iCE40 SB_MAC16 model ...

Signed-off-by: Clifford Wolf <[email protected]>

2019-02-20 12:55:20 +01:00

..

tests

Improve iCE40 SB_MAC16 model

2019-02-20 12:55:20 +01:00

.gitignore

Initialization support for all iCE40 bram modes

2015-04-26 08:39:31 +02:00

arith_map.v

Fixed trailing whitespaces

2015-07-02 11:14:30 +02:00

brams_init.py

Switched to Python 3

2015-08-22 09:59:33 +02:00

brams_map.v

Fixed WE/RE usage in iCE40 BRAM mapping

2015-11-24 10:51:34 +01:00

brams.txt

Added read-enable to memory model

2015-09-25 12:23:11 +02:00

cells_map.v

Improving vpr output support.

2018-04-18 16:55:12 -07:00

cells_sim.v

Improve iCE40 SB_MAC16 model

2019-02-20 12:55:20 +01:00

ice40_ffinit.cc

Consistent use of 'override' for virtual methods in derived classes.

2018-07-20 23:51:06 -07:00

ice40_ffssr.cc

ice40: Honor the "dont_touch" attribute in FFSSR pass

2018-12-08 22:46:28 +01:00

ice40_opt.cc

Extract ice40_unlut pass from ice40_opt.

2018-12-05 16:30:24 +00:00

ice40_unlut.cc

Extract ice40_unlut pass from ice40_opt.

2018-12-05 16:30:24 +00:00

latches_map.v

Added synth_ice40 support for latches via logic loops

2016-05-06 23:02:37 +02:00

Makefile.inc

Extract ice40_unlut pass from ice40_opt.

2018-12-05 16:30:24 +00:00

synth_ice40.cc

Merge pull request #772 from whitequark/synth_lut

2019-01-02 15:44:57 +01:00