Marcin Kościelnicki 7a9081440c xilinx: Add simulation models for MULT18X18* and DSP48A*. ...

This adds simulation models for the following primitives:

- MULT18X18 and MULT18X18S (Virtex 2*, Spartan 3)
- MULT18X18SIO (Spartan 3E, Spartan 3A)
- DSP48A (Spartan 3A DSP) — implemented in terms of DSP48A1
- DSP48A1 (Spartan 6)

2019-11-19 01:00:58 +01:00

..

achronix

Revert "synth_* with -retime option now calls abc with -D 1 as well"

2019-04-18 07:59:16 -07:00

anlogic

make note that it is for latch mode

2019-09-18 17:48:16 +02:00

common

Do not map $eq and $ne in cmp2lut, only proper arithmetic cmp

2019-11-11 15:07:29 +01:00

coolrunner2

Fix spacing

2019-08-06 16:47:55 -07:00

easic

Revert "synth_* with -retime option now calls abc with -D 1 as well"

2019-04-18 07:59:16 -07:00

ecp5

ecp5: Use new autoname pass for better cell/net names

2019-11-15 21:03:11 +00:00

efinix

FF should be initialized to 0

2019-10-04 13:27:10 +02:00

gowin

Fix formatting for msys2 mingw build using GetSize

2019-08-01 17:27:34 +02:00

greenpak4

Revert "synth_* with -retime option now calls abc with -D 1 as well"

2019-04-18 07:59:16 -07:00

ice40

Merge pull request #1490 from YosysHQ/clifford/autoname

2019-11-14 18:03:44 +01:00

intel

techlibs/intel: Clean up Makefile

2019-08-05 11:22:11 -07:00

sf2

Revert "synth_* with -retime option now calls abc with -D 1 as well"

2019-04-18 07:59:16 -07:00

xilinx

xilinx: Add simulation models for MULT18X18* and DSP48A*.

2019-11-19 01:00:58 +01:00

.gitignore

added .gitignore files

2013-01-05 11:19:11 +01:00