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79448f9be035c88589b4e9c0de6b2bdc5acbd4df
yosys
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tests
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arch
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Eddie Hung
c2c74f9bb0
Merge pull request
#1599
from YosysHQ/eddie/retry_1588
...
Retry
#1588
-- "write_xaiger: only instantiate each whitebox cell type once"
2019-12-30 10:01:02 -08:00
..
anlogic
Rename memory tests to lutram, add more xilinx tests
2019-12-12 17:44:37 -08:00
common
Merge pull request
#1574
from YosysHQ/eddie/xilinx_lutram
2019-12-16 21:48:21 -08:00
ecp5
Merge pull request
#1599
from YosysHQ/eddie/retry_1588
2019-12-30 10:01:02 -08:00
efinix
Rename memory tests to lutram, add more xilinx tests
2019-12-12 17:44:37 -08:00
gowin
Rename memory tests to lutram, add more xilinx tests
2019-12-12 17:44:37 -08:00
ice40
Add
#1598
testcase
2019-12-27 16:44:57 -08:00
xilinx
Add
#1598
testcase
2019-12-27 16:44:57 -08:00
run-test.sh
Add simcells.v, simlib.v, and some output
2019-06-27 11:13:49 -07:00