Logo
Explore Help
Sign In
luke/yosys
Watch 1
Star 0
Fork 0
mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-03 03:13:21 +02:00
Code Issues Packages Projects Releases Wiki Activity
Files
78fd24f40f1e2be64e8ea8116a8a2277cb3a9baf
yosys/techlibs/greenpak4
T
History
Andrew Zonenberg cbdddc3af9 greenpak4_counters: Changed generation of primitive names so that the absorbed register's name is included
2017-06-24 14:54:07 -07:00
..
cells_latch.v
greenpak4: Can now techmap inferred D latches (without set/reset or output inverter)
2016-12-10 18:46:36 +08:00
cells_map.v
Initial implementation of techlib support for GreenPAK latches. Instantiation only, no behavioral inference yet.
2016-12-05 21:22:41 -08:00
cells_sim.v
greenpak4: Added POUT to GP_COUNTx cells
2017-01-01 00:56:20 -08:00
gp_dff.lib
Fixed indenting in techlibs/greenpak4/gp_dff.lib
2016-03-29 13:44:14 +02:00
greenpak4_counters.cc
greenpak4_counters: Changed generation of primitive names so that the absorbed register's name is included
2017-06-24 14:54:07 -07:00
greenpak4_dffinv.cc
greenpak4: Added support for inferred input/output inverters on latches
2016-12-10 19:58:32 +08:00
Makefile.inc
greenpak4: Can now techmap inferred D latches (without set/reset or output inverter)
2016-12-10 18:46:36 +08:00
synth_greenpak4.cc
Fix double-call of log_pop() in synth_greenpak4
2017-02-14 11:57:54 +01:00
Powered by Gitea Version: 1.27.2 Page: 78ms Template: 2ms
Auto
English
Bahasa Indonesia Deutsch English Español Français Gaeilge Italiano Latviešu Magyar nyelv Nederlands Polski Português de Portugal Português do Brasil Suomi Svenska Türkçe Čeština Ελληνικά Български Русский Українська فارسی മലയാളം 日本語 简体中文 繁體中文(台灣) 繁體中文(香港) 한국어
Licenses API