This website requires JavaScript.
Explore
Help
Sign In
luke
/
yosys
Watch
1
Star
0
Fork
0
mirror of
https://github.com/YosysHQ/yosys.git
synced
2026-08-30 09:58:22 +02:00
Code
Issues
Packages
Projects
Releases
Wiki
Activity
Files
78fd24f40f1e2be64e8ea8116a8a2277cb3a9baf
yosys
/
examples
/
intel
/
MAX10
T
History
Larry Doolittle
2021ddecb3
Squelch trailing whitespace
2017-04-12 15:11:09 +02:00
..
run_max10
Add initial support for both MAX10 and Cyclone IV (E|GX) FPGAs
2017-04-05 23:01:29 -05:00
runme_postsynth
Add initial support for both MAX10 and Cyclone IV (E|GX) FPGAs
2017-04-05 23:01:29 -05:00
sevenseg.v
Squelch trailing whitespace
2017-04-12 15:11:09 +02:00
top.v
Squelch trailing whitespace
2017-04-12 15:11:09 +02:00