Icenowy Zheng 7854d5ba21 anlogic: fix dbits of Anlogic Eagle DRAM16X4 ... The dbits of DRAM16X4 is wrong set to 2, which leads to waste of DRAM bits. Fix the dbits number in the RAM configuration. Signed-off-by: Icenowy Zheng <icenowy@aosc.io>		2018-12-18 14:38:44 +08:00
..
achronix	…
anlogic	anlogic: fix dbits of Anlogic Eagle DRAM16X4	2018-12-18 14:38:44 +08:00
common	gate2lut: new techlib, for converting Yosys gates to FPGA LUTs.	2018-12-05 17:13:27 +00:00
coolrunner2	…
easic	…
ecp5	ecp5: Add 'fake' DCU parameters	2018-11-09 18:25:42 +00:00
gowin	Changes in GoWin synth commands and ALU primitive support	2018-12-03 20:08:35 -06:00
greenpak4	…
ice40	Rename "fine:" label to "map:" in "synth_ice40"	2018-12-16 16:36:19 +01:00
intel	Changes in GoWin synth commands and ALU primitive support	2018-12-03 20:08:35 -06:00
sf2	Fix sf2 LUT interface	2018-10-31 15:36:53 +01:00
xilinx	Add support for Xilinx PS7 block	2018-11-10 12:45:07 -08:00
.gitignore	…