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whitequark f8d5920a7e Merge pull request #1604 from whitequark/unify-ram-naming

Harmonize BRAM/LUTRAM descriptions across all of Yosys

2020-01-02 21:06:17 +00:00

..

synth_intel: a10gx -> arria10gx

2019-12-10 13:48:10 +00:00

intel: Map M9K BRAM only on families that have it

2019-07-23 18:11:11 +01:00

synth_intel: cyclone10 -> cyclone10lp

2019-12-10 13:47:58 +00:00

Fixed broken Quartus backend on dffeas init value (Error (12170): Illegal value for the POWER_UP parameter. Fixed and tested Cyclone V device

2018-03-31 22:48:47 -06:00

Reduce amount of trailing whitespace in code base

2019-02-28 14:58:11 -08:00

Fixing issues in CycloneV cell sim

2019-04-11 19:59:03 -05:00

Fixed broken Quartus backend on dffeas init value (Error (12170): Illegal value for the POWER_UP parameter. Fixed and tested Cyclone V device

2018-03-31 22:48:47 -06:00

Makefile.inc

synth_intel: a10gx -> arria10gx

2019-12-10 13:48:10 +00:00

synth_intel.cc

Merge pull request #1604 from whitequark/unify-ram-naming

2020-01-02 21:06:17 +00:00