mirror of https://github.com/YosysHQ/yosys.git
23 lines
344 B
Plaintext
23 lines
344 B
Plaintext
logger -expect error "Second design missing module top_renamed" 1
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read_rtlil <<EOT
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module \top
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wire width 1 input 1 \a
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wire width 1 output 2 \y
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connect \y \a
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end
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EOT
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design -save golden
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design -reset
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read_rtlil <<EOT
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module \top_renamed
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wire width 1 input 1 \a
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wire width 1 output 2 \y
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connect \y \a
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end
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EOT
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design_equal golden
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