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mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-04 19:31:00 +02:00
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74d0f17fd4b26eeece7133cf2425d3c4e0e35976
yosys/passes
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Robert Ou 74d0f17fd4 recover_reduce: Reindent using tabs
2017-08-27 02:12:41 -07:00
..
cmds
More intuitive handling of "cd .." for singleton modules
2017-08-19 00:15:12 +02:00
equiv
Fix equiv_simple, old behavior now available with "equiv_simple -short"
2017-04-28 18:57:53 +02:00
fsm
Remove some dead code from fsm_map
2017-08-21 15:02:16 +02:00
hierarchy
Rename "singleton" pass to "uniquify"
2017-08-20 12:31:50 +02:00
memory
Typo fix.
2016-09-08 10:57:16 +03:00
opt
Don't track , ... contradictions through x/z-bits
2017-08-25 16:18:17 +02:00
proc
Added $global_clock verilog syntax support for creating $ff cells
2016-10-14 12:33:56 +02:00
sat
Rename "singleton" pass to "uniquify"
2017-08-20 12:31:50 +02:00
techmap
recover_reduce: Reindent using tabs
2017-08-27 02:12:41 -07:00
tests
Add $live and $fair cell types, add support for s_eventually keyword
2017-02-25 10:36:39 +01:00
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