yosys/tests/various
Eddie Hung db27f2f378
Merge pull request #1973 from YosysHQ/eddie/fix1966
tests: fix various/plugin.sh when PREFIX != /usr/local/share
2020-04-22 10:19:30 -07:00
..
dynamic_part_select Modifications of tests as per Eddie's request 2020-04-20 12:45:35 -05:00
.gitignore tests: add a quick plugin test 2020-04-09 09:45:20 -07:00
abc9.v
abc9.ys abc9: add testcase reduced from #1970 2020-04-20 09:38:29 -07:00
async.sh
async.v
attrib05_port_conn.v
attrib05_port_conn.ys
attrib07_func_call.v
attrib07_func_call.ys
autoname.ys
bug1496.ys
bug1531.ys
bug1614.ys
bug1710.ys
bug1745.ys
bug1781.ys fsm_extract: Initialize celltypes with full design. 2020-03-19 18:51:21 +01:00
bug1876.ys tests: add testcases from #1876 2020-04-14 12:39:10 -07:00
chparam.sh
constcomment.ys
constmsk_test.v
constmsk_test.ys
constmsk_testmap.v
deminout_unused.ys
design.ys design: add test 2020-04-16 12:48:40 -07:00
design1.ys design: add test 2020-04-16 12:48:40 -07:00
design2.ys tests: add design -delete tests 2020-04-16 08:05:18 -07:00
dynamic_part_select.ys Remove '-ignore_unknown_cells' option from 'sat' 2020-04-20 11:58:23 -07:00
elab_sys_tasks.sv
elab_sys_tasks.ys
equiv_opt_multiclock.ys
exec.ys Add test for `exec` command. 2020-03-16 07:52:58 +00:00
global_scope.ys ast: Fix handling of identifiers in the global scope 2020-04-16 10:30:07 +01:00
gzip_verilog.v.gz
gzip_verilog.ys
help.ys
hierarchy.sh
hierarchy_defer.ys
hierarchy_param.ys hierarchy: Convert positional parameters to named. 2020-04-21 19:09:00 +02:00
ice40_mince_abc9.ys Add test for abc9+mince issue 2020-03-20 20:35:28 +00:00
logger_error.ys
logger_nowarning.ys
logger_warn.ys
logger_warning.ys
mem2reg.ys
muxcover.ys
muxpack.v
muxpack.ys
peepopt.ys
plugin.cc tests: add a quick plugin test 2020-04-09 09:45:20 -07:00
plugin.sh tests: use `yosys-config --datdir` instead of hard-coded 2020-04-22 08:29:45 -07:00
pmgen_reduce.ys
pmux2shiftx.v
pmux2shiftx.ys
reg_wire_error.sv
reg_wire_error.ys
run-test.sh
scratchpad.ys
script.ys
sformatf.ys
shregmap.v
shregmap.ys
signext.ys
sim_const.ys sim: Fix handling of constant-connected cell inputs at startup 2020-04-21 08:58:52 +01:00
specify.v
specify.ys
src.ys
submod.ys
submod_extract.ys
sv_defines.ys Add support for SystemVerilog-style `define to Verilog frontend 2020-03-27 16:08:26 +00:00
sv_defines_dup.ys Add support for SystemVerilog-style `define to Verilog frontend 2020-03-27 16:08:26 +00:00
sv_defines_mismatch.ys Add support for SystemVerilog-style `define to Verilog frontend 2020-03-27 16:08:26 +00:00
sv_defines_too_few.ys Add support for SystemVerilog-style `define to Verilog frontend 2020-03-27 16:08:26 +00:00
sv_implicit_ports.sh
svalways.sh
wreduce.ys
write_gzip.ys