mirror of https://github.com/YosysHQ/yosys.git
14 lines
386 B
Python
14 lines
386 B
Python
from pathlib import Path
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from pyosys import libyosys as ys
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__file_dir__ = Path(__file__).absolute().parent
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src = __file_dir__.parent / "simple" / "fiedler-cooley.v"
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design = ys.Design()
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design.run_pass(["read_verilog", str(src)])
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design.run_pass("hierarchy -top up3down5")
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design.run_pass(["proc"])
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design.run_pass("opt -full")
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design.run_pass("select -assert-mod-count 1 up3down5")
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