mirror of https://github.com/YosysHQ/yosys.git
write_verilog: write $tribuf cell as ternary |
||
|---|---|---|
| .. | ||
| Makefile.inc | ||
| verilog_backend.cc | ||
write_verilog: write $tribuf cell as ternary |
||
|---|---|---|
| .. | ||
| Makefile.inc | ||
| verilog_backend.cc | ||