yosys/backends/verilog
Clifford Wolf 81581f24fc
Merge pull request #800 from whitequark/write_verilog_tribuf
write_verilog: write $tribuf cell as ternary
2019-01-27 09:23:41 +01:00
..
Makefile.inc initial import 2013-01-05 11:13:26 +01:00
verilog_backend.cc Merge pull request #800 from whitequark/write_verilog_tribuf 2019-01-27 09:23:41 +01:00