mirror of https://github.com/YosysHQ/yosys.git
verlog: allow shadowing module ports within generate blocks |
||
|---|---|---|
| .. | ||
| aiger | ||
| ast | ||
| blif | ||
| json | ||
| liberty | ||
| rpc | ||
| rtlil | ||
| verific | ||
| verilog | ||
verlog: allow shadowing module ports within generate blocks |
||
|---|---|---|
| .. | ||
| aiger | ||
| ast | ||
| blif | ||
| json | ||
| liberty | ||
| rpc | ||
| rtlil | ||
| verific | ||
| verilog | ||