yosys

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garytwong 834a7294b7 verilog: fix string literal regular expression (#5187 )

* verilog: fix string literal regular expression.

A backslash was improperly quoted, causing string literal matching
to fail when the final token before a closing quote was an escaped
backslash.

* verilog: add regression test for string literal regex bug.

Test for bug triggered by escaped backslash immediately before
closing quote (introduced in ca7d94af and fixed by 40aa7eaf).

2025-06-19 12:41:18 -04:00

aiger

rtlil: represent Const strings as std::string

2024-10-14 06:28:12 +02:00

aiger2

aiger2: Clean debug print

2024-12-10 14:27:55 +01:00

ast

Merge pull request #5163 from YosysHQ/emil/fix-single-bit-vector-leak

2025-06-04 17:00:54 +02:00

blif

rtlil: represent Const strings as std::string