mirror of https://github.com/YosysHQ/yosys.git
16 lines
321 B
Plaintext
16 lines
321 B
Plaintext
# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
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autoidx 1
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module \gold
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wire input 1 \CI
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wire width 2 output 2 \CO
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wire width 2 input 3 \G
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wire width 2 input 4 \P
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cell $lcu \UUT
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parameter \WIDTH 2
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connect \CI \CI
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connect \CO \CO
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connect \G \G
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connect \P \P
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end
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end
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