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mirror of https://github.com/YosysHQ/yosys.git synced 2026-10-07 02:23:09 +02:00
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6fcbc79b5c53c85dfbf37eba6ef8d8b3f7f7b1c7
yosys/techlibs/common
T
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Clifford Wolf 6fcbc79b5c Improved width extension with regard to undef propagation
2013-11-06 21:05:11 +01:00
..
blackbox.sed
Moved common techlib files to techlibs/common
2013-09-15 11:52:57 +02:00
Makefile.inc
Moved common techlib files to techlibs/common
2013-09-15 11:52:57 +02:00
simlib.v
Added $sr, $dffsr and $dlatch cell types
2013-10-18 11:56:16 +02:00
stdcells_sim.v
Added $_SR_[PN][PN]_, $_DFFSR_[PN][PN][PN]_, $_DLATCH_[PN]_
2013-10-18 12:13:34 +02:00
stdcells.v
Improved width extension with regard to undef propagation
2013-11-06 21:05:11 +01:00
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