yosys/techlibs at 6fa8ce93e673177b50888aa94d7f1c8b221d9b10 - yosys - Gitea: Git with a cup of tea

luke/yosys

mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-04 11:29:42 +02:00

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whitequark 6fa8ce93e6 ecp5: add missing FD primitives.

2019-08-30 09:54:48 +00:00

..

Revert "synth_* with -retime option now calls abc with -D 1 as well"

2019-04-18 07:59:16 -07:00

Fix missing newline at end of file

2019-08-22 18:09:37 +02:00

Missing newline

2019-08-20 20:37:52 -07:00

Fix spacing

2019-08-06 16:47:55 -07:00

Revert "synth_* with -retime option now calls abc with -D 1 as well"

2019-04-18 07:59:16 -07:00

ecp5: add missing FD primitives.

2019-08-30 09:54:48 +00:00

Fix missing newline at end of file

2019-08-22 18:06:36 +02:00

Fix formatting for msys2 mingw build using GetSize

2019-08-01 17:27:34 +02:00

Revert "synth_* with -retime option now calls abc with -D 1 as well"

2019-04-18 07:59:16 -07:00

Rename boxes too

2019-08-29 07:03:32 -07:00

techlibs/intel: Clean up Makefile

2019-08-05 11:22:11 -07:00

Revert "synth_* with -retime option now calls abc with -D 1 as well"

2019-04-18 07:59:16 -07:00

Add (* clkbuf_sink *) to SRLC16E, reorder ports to match vendor

2019-08-28 10:51:39 -07:00

.gitignore

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