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6f9c515a222b322d8d3605e09eb69e7023e61e70
yosys
/
tests
/
memlib
T
History
Miodrag Milanovic
91e41d8c80
Move parameters to module declaration
2024-04-08 12:44:37 +02:00
..
.gitignore
…
generate.py
memory_libmap: look for ram_style attributes on surrounding signals
2023-10-19 19:23:35 +02:00
memlib_9b1B.txt
…
memlib_9b1B.v
Move parameters to module declaration
2024-04-08 12:44:37 +02:00
memlib_block_sdp_1clk.txt
…
memlib_block_sdp_1clk.v
…
memlib_block_sdp.txt
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memlib_block_sdp.v
…
memlib_block_sp_full.txt
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memlib_block_sp_full.v
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memlib_block_sp.txt
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memlib_block_sp.v
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memlib_block_tdp.txt
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memlib_block_tdp.v
…
memlib_clock_sdp.txt
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memlib_clock_sdp.v
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memlib_lut.txt
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memlib_lut.v
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memlib_multilut.txt
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memlib_multilut.v
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memlib_wide_read.txt
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memlib_wide_read.v
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memlib_wide_sdp.txt
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memlib_wide_sdp.v
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memlib_wide_sp.txt
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memlib_wide_sp.v
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memlib_wide_write.txt
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memlib_wide_write.v
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memlib_wren.txt
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memlib_wren.v
Move parameters to module declaration
2024-04-08 12:44:37 +02:00
run-test.sh
…
