Eddie Hung 505557e93e Merge pull request #1576 from YosysHQ/eddie/opt_merge_init ... opt_merge: discard \init of '$' cells with 'Q' port when merging		2020-02-05 14:56:26 -08:00
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cmds	redirect fuser stderr to /dev/null	2020-01-28 10:02:41 +01:00
equiv	xilinx: Add xilinx_dffopt pass (#1557)	2019-12-18 13:43:43 +01:00
fsm	fsm_detect: Add a cache to avoid excessive CPU usage for big mux networks.	2020-01-14 22:49:20 +01:00
hierarchy	sv: Improve handling of wildcard port connections	2020-02-02 16:12:33 +00:00
memory	Cleanup	2019-12-17 00:25:08 -08:00
opt	Merge pull request #1576 from YosysHQ/eddie/opt_merge_init	2020-02-05 14:56:26 -08:00
pmgen	Merge pull request #1657 from YosysHQ/dave/xilinx-dsp-multonly	2020-02-02 14:53:32 +00:00
proc	proc_dlatch: Add error handling for incorrect always_(ff|latch|comb) usage	2019-11-21 20:46:41 +00:00
sat	Merge pull request #1638 from YosysHQ/eddie/fix1631	2020-02-05 19:31:18 +01:00
techmap	abc9_ops: -reintegrate to use derived_type for box_ports	2020-02-05 14:46:48 -08:00
tests	Document (* gentb_skip *) attr for test_autotb	2019-09-18 12:41:35 -07:00