mirror of https://github.com/YosysHQ/yosys.git
47 lines
821 B
Plaintext
47 lines
821 B
Plaintext
read_verilog <<EOT
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module add8(
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input [15:0] a, b, c, d, e, f, g, h,
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output [15:0] y
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);
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assign y = a + b + c + d + e + f + g + h;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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arith_tree
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select -assert-count 6 t:$fa
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select -assert-count 1 t:$add
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arith_tree
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select -assert-count 6 t:$fa
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select -assert-count 1 t:$add
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select -assert-none t:$sub
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design -reset
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read_verilog <<EOT
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module macc_idempotent(
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input [15:0] a, b, c, d, e, f, g, h,
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output [15:0] y
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);
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assign y = a + b + c + d + e + f + g + h;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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alumacc
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opt_clean
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arith_tree
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select -assert-count 6 t:$fa
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select -assert-count 1 t:$add
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select -assert-none t:$sub
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select -assert-none t:$alu
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arith_tree
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select -assert-count 6 t:$fa
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select -assert-count 1 t:$add
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select -assert-none t:$sub
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select -assert-none t:$alu
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design -reset
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