Clifford Wolf b6bd12fade Add error for cell output ports that are connected to constants

2017-07-22 15:08:30 +02:00

..

cmds

Add $alu to list of supported cells for "stat -width"

2017-07-14 11:32:49 +02:00

equiv

Fix equiv_simple, old behavior now available with "equiv_simple -short"

2017-04-28 18:57:53 +02:00

fsm

Squelch trailing whitespace

2017-04-12 15:11:09 +02:00

hierarchy

Add error for cell output ports that are connected to constants

2017-07-22 15:08:30 +02:00

memory

Typo fix.

2016-09-08 10:57:16 +03:00

opt

Excluded $_TBUF_ from opt_merge pass

2017-07-03 13:21:20 -03:00

proc

Added $global_clock verilog syntax support for creating $ff cells

2016-10-14 12:33:56 +02:00

sat

Add "setundef -anyseq"

2017-05-28 11:59:05 +02:00

techmap

Fix handling of empty cell port assignments (i.e. ignore them)

2017-07-21 19:32:31 +02:00

tests

Add $live and $fair cell types, add support for s_eventually keyword

2017-02-25 10:36:39 +01:00