Logo
Explore Help
Sign In
luke/yosys
Watch 1
Star 0
Fork 0
mirror of https://github.com/YosysHQ/yosys.git synced 2026-10-06 18:13:40 +02:00
Code Issues Packages Projects Releases Wiki Activity
Files
6d7a77dbf6fca96efec4e87a5755d7c3a2f6af2a
yosys/passes
T
History
Clifford Wolf cf25dc9ce7 Copy attributes to _TECHMAP_REPLACE_ cells
2017-02-16 12:28:42 +01:00
..
cmds
Added "check -initdrv"
2017-01-04 18:12:41 +01:00
equiv
Add $ff and $_FF_ support to equiv_simple
2017-01-30 10:50:38 +01:00
fsm
Be more conservative with merging large cells into FSMs
2017-01-26 09:19:28 +01:00
hierarchy
Do not fix port widths on any blackbox instances
2017-02-13 17:07:38 +01:00
memory
Typo fix.
2016-09-08 10:57:16 +03:00
opt
Fixed some "used uninitialized" warnings in opt_expr
2017-02-11 10:50:48 +01:00
proc
Added $global_clock verilog syntax support for creating $ff cells
2016-10-14 12:33:56 +02:00
sat
Bugfix in "miter -assert" handling of assumptions
2016-10-17 14:56:58 +02:00
techmap
Copy attributes to _TECHMAP_REPLACE_ cells
2017-02-16 12:28:42 +01:00
tests
Cosmetic fix in test_autotb.cc
2016-09-19 20:43:43 +02:00
Powered by Gitea Version: 1.27.2 Page: 63ms Template: 2ms
Auto
English
Bahasa Indonesia Deutsch English Español Français Gaeilge Italiano Latviešu Magyar nyelv Nederlands Polski Português de Portugal Português do Brasil Suomi Svenska Türkçe Čeština Ελληνικά Български Русский Українська فارسی മലയാളം 日本語 简体中文 繁體中文(台灣) 繁體中文(香港) 한국어
Licenses API