mirror of https://github.com/YosysHQ/yosys.git
c36cf9c5ac
The Verilog grammar does not allow an empty case. Most synthesis tools are quite permissive about this, but Quartus is not. This causes problems for amaranth with Quartus (see amaranth-lang/amaranth#931). |
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| .. | ||
| aiger | ||
| blif | ||
| btor | ||
| cxxrtl | ||
| edif | ||
| firrtl | ||
| intersynth | ||
| jny | ||
| json | ||
| rtlil | ||
| simplec | ||
| smt2 | ||
| smv | ||
| spice | ||
| table | ||
| verilog | ||