Clifford Wolf 6bbe2fdbf3 Add splitcmplxassign test case and silence splitcmplxassign warning ...

Signed-off-by: Clifford Wolf <[email protected]>

2019-05-01 10:01:54 +02:00

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aiger

Add tests/aiger/.gitignore

2019-04-19 14:04:12 +02:00

asicworld

Fix FIRRTL to Verilog process instance subfield assignment.

2019-02-25 16:18:13 -08:00

bram

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errors

Rename the generic "Syntax error" message from the Verilog/SystemVerilog parser into unique,

2018-10-25 02:37:56 +03:00

fsm

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hana

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liberty

Liberty file parser now accepts superfluous ;

2019-03-27 15:16:19 +01:00

lut

cmp2lut: new techmap pass.

2019-01-02 07:53:31 +00:00

memories

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opt

Fix WREDUCE on FF not fixing ARST_VALUE parameter.

2019-02-22 10:30:42 -08:00

realmath

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sat

support repeat loops with constant repeat counts outside of constant functions

2019-04-09 12:28:32 -04:00

share

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simple

Add splitcmplxassign test case and silence splitcmplxassign warning

2019-05-01 10:01:54 +02:00

smv

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sva

Fix "verific -extnets" for more complex situations

2019-03-26 14:17:46 +01:00

svinterfaces

Add missing .gitignore

2018-12-06 07:29:37 +01:00

techmap

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tools

Fix tests

2019-04-21 11:40:20 +02:00

unit

Build hotfix in tests/unit/Makefile

2016-12-11 10:58:49 +01:00

various

Updaye pmux2shiftx test

2019-04-22 16:17:43 +02:00

vloghtb

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