mirror of https://github.com/YosysHQ/yosys.git
105 lines
2.0 KiB
Plaintext
105 lines
2.0 KiB
Plaintext
log -header "Simple positive case"
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log -push
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design -reset
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read_verilog <<EOF
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module top(a, b, y);
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input wire signed [7:0] a;
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input wire signed [7:0] b;
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output wire signed [7:0] y;
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assign y = a - b;
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endmodule
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EOF
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proc; opt
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check -assert
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equiv_opt -assert negopt -pre
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design -load postopt
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select -assert-count 1 t:$add
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select -assert-count 1 t:$neg
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select -assert-none t:$sub
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design -reset
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log -pop
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log -header "Unsigned positive case"
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log -push
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design -reset
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read_verilog <<EOF
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module top(a, b, y);
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input wire [7:0] a;
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input wire [7:0] b;
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output wire [7:0] y;
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assign y = a - b;
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endmodule
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EOF
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proc; opt
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check -assert
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equiv_opt -assert negopt -pre
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design -load postopt
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select -assert-count 1 t:$add
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select -assert-count 1 t:$neg
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select -assert-none t:$sub
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design -reset
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log -pop
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log -header "Negative case: constant subtrahend"
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log -push
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design -reset
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read_verilog <<EOF
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module top(a, y);
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input wire signed [7:0] a;
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output wire signed [7:0] y;
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assign y = a - 8'd5;
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endmodule
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EOF
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proc; opt
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check -assert
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equiv_opt -assert negopt -pre
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design -load postopt
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# Should NOT transform because constant subtraction is kept as $sub
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select -assert-count 1 t:$sub
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select -assert-none t:$add
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select -assert-none t:$neg
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design -reset
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log -pop
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log -header "Anchor case: output wider than inputs"
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log -push
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design -reset
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read_verilog <<EOF
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module top(a, b, y);
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input wire signed [7:0] a;
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input wire signed [7:0] b;
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output wire signed [11:0] y;
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assign y = a - b;
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endmodule
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EOF
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proc; opt
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check -assert
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equiv_opt -assert negopt -pre
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design -load postopt
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select -assert-count 1 t:$add
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select -assert-count 1 t:$neg
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select -assert-none t:$sub
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design -reset
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log -pop
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log -header "Signedness case"
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log -push
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design -reset
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read_verilog <<EOF
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module top(a, b, y);
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input wire signed [7:0] a;
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input wire [7:0] b;
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output wire signed [7:0] y;
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assign y = a - b;
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endmodule
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EOF
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proc; opt
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check -assert
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equiv_opt -assert negopt -pre
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design -load postopt
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select -assert-count 1 t:$add
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select -assert-count 1 t:$neg
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select -assert-none t:$sub
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design -reset
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log -pop
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