mirror of https://github.com/YosysHQ/yosys.git
111 lines
2.2 KiB
Plaintext
111 lines
2.2 KiB
Plaintext
log -header "Simple positive case (same width)"
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log -push
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design -reset
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read_verilog <<EOF
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module top(a, b, y);
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input wire signed [7:0] a;
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input wire signed [7:0] b;
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output wire signed [7:0] y;
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assign y = (-a) + (-b);
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endmodule
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EOF
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proc; opt
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check -assert
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equiv_opt -assert negopt -post
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design -load postopt
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select -assert-count 1 t:$add
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select -assert-count 1 t:$neg
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select -assert-none t:$sub
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design -reset
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log -pop
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log -header "Unsigned positive case"
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log -push
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design -reset
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read_verilog <<EOF
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module top(a, b, y);
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input wire [7:0] a;
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input wire [7:0] b;
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output wire [7:0] y;
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assign y = (-a) + (-b);
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endmodule
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EOF
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proc; opt
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check -assert
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equiv_opt -assert negopt -post
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design -load postopt
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select -assert-count 1 t:$add
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select -assert-count 1 t:$neg
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select -assert-none t:$sub
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design -reset
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log -pop
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log -header "Anchor case: neg branches with different widths"
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log -push
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design -reset
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read_verilog <<EOF
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module top(a, b, y);
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input wire signed [7:0] a;
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input wire signed [9:0] b;
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output wire signed [11:0] y;
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wire signed [5:0] n1;
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wire signed [7:0] n2;
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assign n1 = -a[5:0];
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assign n2 = -b[7:0];
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assign y = n1 + n2;
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endmodule
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EOF
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proc; opt
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check -assert
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equiv_opt -assert negopt -post
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design -load postopt
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select -assert-count 1 t:$add
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select -assert-none t:$sub
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design -reset
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log -pop
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log -header "Negative case: signedness mismatch on negations"
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log -push
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design -reset
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read_verilog <<EOF
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module top(a, b, y);
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input wire signed [7:0] a;
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input wire [7:0] b;
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output wire signed [7:0] y;
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assign y = (-a) + (-b);
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endmodule
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EOF
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proc; opt
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check -assert
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equiv_opt -assert negopt -post
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design -load postopt
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select -assert-count 1 t:$add
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select -assert-none t:$sub
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design -reset
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log -pop
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log -header "Negative case: add input not direct neg output"
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log -push
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design -reset
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read_verilog <<EOF
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module top(a, b, y);
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input wire signed [7:0] a;
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input wire signed [7:0] b;
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output wire signed [7:0] y;
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wire signed [7:0] na;
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wire signed [7:0] nb;
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assign na = -a;
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assign nb = -b;
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assign y = (na ^ 8'h00) + nb;
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endmodule
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EOF
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proc; opt
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check -assert
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equiv_opt -assert negopt -post
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design -load postopt
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select -assert-count 1 t:$add
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select -assert-count 2 t:$neg
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select -assert-none t:$sub
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design -reset
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log -pop
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