yosys/techlibs at 6b314c8371bbd8bb999f5ad330aa71c803755d54 - yosys - Gitea: Git with a cup of tea

luke/yosys

mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-03 03:13:21 +02:00

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Eddie Hung 6b314c8371 Wrap SB_CARRY+SB_LUT into $__ICE40_FULL_ADDER

2019-08-07 16:29:38 -07:00

..

Revert "synth_* with -retime option now calls abc with -D 1 as well"

2019-04-18 07:59:16 -07:00

anlogic : Fix alu mapping

2019-08-03 14:47:33 +02:00

Add $_NMUX_, add "abc -g cmos", add proper cmos cell costs

2019-08-06 04:47:55 +02:00

Revert "synth_* with -retime option now calls abc with -D 1 as well"

2019-04-18 07:59:16 -07:00

Revert "synth_* with -retime option now calls abc with -D 1 as well"

2019-04-18 07:59:16 -07:00

ecp5: Make cells_sim.v consistent with nextpnr

2019-08-07 14:19:31 +01:00

Fix formatting for msys2 mingw build using GetSize

2019-08-01 17:27:34 +02:00

Revert "synth_* with -retime option now calls abc with -D 1 as well"

2019-04-18 07:59:16 -07:00

Wrap SB_CARRY+SB_LUT into $__ICE40_FULL_ADDER

2019-08-07 16:29:38 -07:00

Merge branch 'ZirconiumX-synth_intel_m9k'

2019-07-25 17:23:48 +02:00

Revert "synth_* with -retime option now calls abc with -D 1 as well"

2019-04-18 07:59:16 -07:00

RST -> RSTBRST for RAMB8BWER

2019-07-29 16:05:44 -07:00

.gitignore

added .gitignore files

2013-01-05 11:19:11 +01:00