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mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-07 04:19:56 +02:00
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6824ee065ae8b2511879aa5edaec0dfe7860fc3f
yosys/techlibs/intel_alm/common
T
History
Miodrag Milanovic a689342207 Remove trailing whitespaces
2026-06-23 07:24:59 +02:00
..
abc9_map.v
Remove trailing whitespaces
2026-06-23 07:24:59 +02:00
abc9_model.v
intel_alm: compose $__MISTRAL_FF_SYNCONLY from MISTRAL_FF
2020-07-04 19:45:10 +02:00
abc9_unmap.v
intel_alm: add $__ prefix to MISTRAL_FF_SYNCONLY
2020-07-04 19:45:10 +02:00
alm_map.v
Add force_downto and force_upto wire attributes.
2020-05-19 01:42:40 +02:00
alm_sim.v
intel_alm: drop quartus support
2024-05-03 11:32:33 +01:00
arith_alm_map.v
intel_alm: Fix illegal carry chains
2021-05-15 22:37:06 +01:00
bram_m10k_map.v
intel_alm: re-enable 8x40-bit M10K support
2023-05-29 06:42:03 +01:00
bram_m10k.txt
intel_alm: re-enable 8x40-bit M10K support
2023-05-29 06:42:03 +01:00
dff_map.v
synth_intel_alm: Use dfflegalize.
2020-07-04 22:56:16 +02:00
dff_sim.v
intel_alm: drop quartus support
2024-05-03 11:32:33 +01:00
dsp_map.v
intel_alm: Add multiply signedness to cells
2020-08-26 22:50:16 +02:00
dsp_sim.v
intel_alm: preliminary Arria V support
2021-11-25 17:20:36 +01:00
lutram_mlab.txt
End of file fix
2026-06-23 07:23:41 +02:00
megafunction_bb.v
Remove trailing whitespaces
2026-06-23 07:24:59 +02:00
mem_sim.v
intel_alm: drop quartus support
2024-05-03 11:32:33 +01:00
misc_sim.v
End of file fix
2026-06-23 07:23:41 +02:00
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