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67b78ea4fbb8b7d2fc36bb66e4e51e0e5c8d7d9a
yosys
/
frontends
/
verilog
T
History
Clifford Wolf
17ceab92a9
Bugfix in Verilog string handling
...
Signed-off-by: Clifford Wolf <
[email protected]
>
2019-01-05 12:10:24 +01:00
..
.gitignore
Add "make coverage"
2018-08-27 14:22:21 +02:00
const2ast.cc
Convert more log_error() to log_file_error() where possible.
2018-07-20 09:37:44 -07:00
Makefile.inc
Add "make coverage"
2018-08-27 14:22:21 +02:00
preproc.cc
Support SystemVerilog `` extension for macros
2018-05-17 00:09:56 -04:00
verilog_frontend.cc
Add "read_verilog -noassert -noassume -assert-assumes"
2018-09-24 20:51:16 +02:00
verilog_frontend.h
Add "read_verilog -noassert -noassume -assert-assumes"
2018-09-24 20:51:16 +02:00
verilog_lexer.l
Bugfix in Verilog string handling
2019-01-05 12:10:24 +01:00
verilog_parser.y
Fix typographical and grammatical errors and inconsistencies.
2019-01-02 13:12:17 +00:00
