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679bc6507f08cab33de0c46b3a96bfaeab2069f4
yosys
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techlibs
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intel
T
History
Clifford Wolf
eb663c7579
Merge branch 'ZirconiumX-synth_intel_m9k'
2019-07-25 17:23:48 +02:00
..
a10gx
…
common
intel: Map M9K BRAM only on families that have it
2019-07-23 18:11:11 +01:00
cyclone10
Fixed broken Quartus backend on dffeas init value (Error (12170): Illegal value for the POWER_UP parameter. Fixed and tested Cyclone V device
2018-03-31 22:48:47 -06:00
cycloneiv
Fixed broken Quartus backend on dffeas init value (Error (12170): Illegal value for the POWER_UP parameter. Fixed and tested Cyclone V device
2018-03-31 22:48:47 -06:00
cycloneive
Reduce amount of trailing whitespace in code base
2019-02-28 14:58:11 -08:00
cyclonev
Fixing issues in CycloneV cell sim
2019-04-11 19:59:03 -05:00
max10
Fixed broken Quartus backend on dffeas init value (Error (12170): Illegal value for the POWER_UP parameter. Fixed and tested Cyclone V device
2018-03-31 22:48:47 -06:00
Makefile.inc
intel: Map M9K BRAM only on families that have it
2019-07-23 18:11:11 +01:00
synth_intel.cc
Merge branch 'ZirconiumX-synth_intel_m9k'
2019-07-25 17:23:48 +02:00
