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luke
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yosys
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675f53abbb7ab4204dc9d9f54fc698a2dc2f15cb
yosys
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techlibs
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Clifford Wolf
9ac560f5d3
Add "dffinit -highlow" and fix synth_intel
...
Signed-off-by: Clifford Wolf <
[email protected]
>
2018-01-09 18:42:19 +01:00
..
achronix
Organizing Speedster file names
2017-11-08 20:23:55 -06:00
common
Fix minor typo in "prep" help message
2017-12-19 21:44:05 +01:00
coolrunner2
coolrunner2: Finish fixing special-use p-terms
2017-09-01 07:22:16 -07:00
easic
Add first draft of eASIC back-end
2017-09-29 17:53:43 +02:00
gowin
…
greenpak4
Added RESET_TO_MAX parameter to $__COUNT_ cell. Cannot yet be extracted.
2017-09-14 10:26:32 -07:00
ice40
Fix port names in SB_IO_OD
2017-12-10 15:33:38 +00:00
intel
Add "dffinit -highlow" and fix synth_intel
2018-01-09 18:42:19 +01:00
xilinx
…
.gitignore
…