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mirror of https://github.com/YosysHQ/yosys.git synced 2026-10-06 18:13:40 +02:00
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675a44b41a2df2c02ceccda2434bc3efac3e5e2f
yosys/passes
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Clifford Wolf 675a44b41a Be slightly less aggressive in "deminout" pass
Signed-off-by: Clifford Wolf <[email protected]>
2018-06-19 14:29:38 +02:00
..
cmds
Include module name for area summary stats
2018-06-18 17:29:01 -07:00
equiv
Improve log messages in equiv_make
2018-01-19 16:20:40 +01:00
fsm
Remove some dead code from fsm_map
2017-08-21 15:02:16 +02:00
hierarchy
Bugfix in handling of array instances with empty ports
2018-05-31 18:09:31 +02:00
memory
Disable memory_dff for initialized FFs
2018-05-28 17:16:15 +02:00
opt
Add optimization of tristate buffer with constant control input
2018-05-12 15:18:27 +02:00
proc
Add warnings for driver-driver conflicts between FFs (and other cells) and constants
2017-12-12 17:13:27 +01:00
sat
Removed $timescale from "sat" command VCD writer
2018-03-29 12:38:41 +02:00
techmap
Be slightly less aggressive in "deminout" pass
2018-06-19 14:29:38 +02:00
tests
Add $live and $fair cell types, add support for s_eventually keyword
2017-02-25 10:36:39 +01:00
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