yosys/frontends at 66bd4716cf31423dcd0174229aed2065de44dad7 - yosys - Gitea: Git with a cup of tea

luke/yosys

mirror of https://github.com/YosysHQ/yosys.git synced 2026-10-06 10:03:36 +02:00

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History

Emil J. Tywoniak ecb8b20f62 yosys: use newcelltypes for yosys_celltypes users

2026-03-04 12:39:44 +01:00

..

yosys: use newcelltypes for yosys_celltypes users

2026-03-04 12:39:44 +01:00

Enable xaiger2 pass when not in NDEBUG

2025-11-21 14:23:32 -08:00

verilog: Do not set module_not_derived on internal cells

2026-01-19 16:48:13 -08:00

blifparse: add bounds check

2026-02-11 12:16:02 +01:00

Support param. default values in JSON FE and SV BE

2026-02-11 08:10:55 -08:00

read_liberty: support loopy retention cells

2025-11-20 13:21:32 +01:00

Remove .c_str() from parameters to log_debug()

2025-09-23 19:10:33 +12:00

Add -legalize option to read_rtlil

2025-12-21 21:47:48 +00:00

Guard vhdl_file::UNDEFINED behind VERIFIC_VHDL_SUPPORT.

2026-02-02 15:26:03 -08:00

read_verilog: remove log I left behind by accident

2026-01-13 18:47:23 +01:00