yosys/passes
Miodrag Milanović 66306a8ca3
Merge pull request #5769 from Silimate/optimize_sim_pass
sim: early return from checkSignals in sim mode
2026-03-23 17:19:26 +00:00
..
cmds Merge pull request #5724 from abhinavputhran/fix/setundef-respect-selection 2026-03-18 22:53:06 +00:00
equiv Merge pull request #5512 from YosysHQ/emil/turbo-celltypes 2026-03-04 14:47:57 +00:00
fsm fsm_detect: add adff detection 2025-11-06 23:29:47 +02:00
hierarchy hierarchy.cc: Tidying 2025-10-15 09:42:47 +13:00
memory memory_libmap: Add -force-params 2026-02-20 10:57:00 +00:00
opt Merge pull request #5664 from rocallahan/parallel-opt-clean 2026-03-16 09:52:34 +00:00
pmgen Remove .c_str() from log_cmd_error() and log_file_error() parameters 2025-09-16 22:59:08 +00:00
proc proc_clean: Removing an empty full_case is doing something 2026-01-07 13:10:32 +13:00
sat sim: early-return from checkSignals in sim mode 2026-03-20 12:32:49 -07:00
techmap Merge pull request #5764 from YosysHQ/emil/constmap-error 2026-03-23 15:15:04 +00:00
tests test_cell.cc: Generate .aag for all compatible cells 2025-12-02 14:03:36 +13:00