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yosys/kernel
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Eddie Hung c90324662c Merge pull request #1828 from YosysHQ/eddie/celltypes_speedup 
kernel: share a single CellTypes within a pass
2020-04-01 14:17:45 -07:00
..
bitpattern.h
…
calc.cc
…
cellaigs.cc
Use more ID::{A,B,Y,blackbox,whitebox}
2019-08-15 14:50:10 -07:00
cellaigs.h
…
celledges.cc
Use more ID::{A,B,Y,blackbox,whitebox}
2019-08-15 14:50:10 -07:00
celledges.h
Consistent use of 'override' for virtual methods in derived classes.
2018-07-20 23:51:06 -07:00
celltypes.h
Use more ID::{A,B,Y,blackbox,whitebox}
2019-08-15 14:50:10 -07:00
consteval.h
Revert "SigSet<Cell*> to use stable compare class"
2019-09-13 09:49:15 -07:00
cost.h
Use ID() in kernel/*, add simple ID:: hack (to be improved upon later)
2019-08-11 11:39:46 +02:00
driver.cc
Add YS_ prefix to macros, add explanation and apply to older version as well
2020-03-13 17:19:54 +01:00
hashlib.h
Add hashlib "<container>::element(int n)" methods
2019-03-14 22:04:42 +01:00
log.cc
Add YS_ prefix to macros, add explanation and apply to older version as well
2020-03-13 17:19:54 +01:00
log.h
exclude clang from checking
2020-03-13 17:23:27 +01:00
macc.h
Use more ID::{A,B,Y,blackbox,whitebox}
2019-08-15 14:50:10 -07:00
modtools.h
kernel: share a single CellTypes within a pass
2020-03-18 12:21:40 -07:00
register.cc
Add ScriptPass::run_nocheck and use for abc9
2020-03-09 14:34:22 +00:00
register.h
Add ScriptPass::run_nocheck and use for abc9
2020-03-09 14:34:22 +00:00
rtlil.cc
Add support for SystemVerilog-style `define to Verilog frontend
2020-03-27 16:08:26 +00:00
rtlil.h
Add support for SystemVerilog-style `define to Verilog frontend
2020-03-27 16:08:26 +00:00
satgen.h
Use more ID::{A,B,Y,blackbox,whitebox}
2019-08-15 14:50:10 -07:00
sigtools.h
Spacing
2019-09-13 16:30:44 -07:00
timinginfo.h
Small fixes
2020-02-27 10:29:53 -08:00
utils.h
…
yosys.cc
Clean up pseudo-private member usage in kernel/yosys.cc.
2020-04-01 02:53:56 +00:00
yosys.h
log_dump() to support State enum
2019-10-02 17:49:07 -07:00