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yosys/backends
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Clifford Wolf e807e88b60 Rename T_{RISE,FALL}_AVG to T_{RISE,FALL}_TYP to better match verilog std nomenclature 
Signed-off-by: Clifford Wolf <[email protected]>
2019-04-23 21:36:59 +02:00
..
aiger
Add "write_aiger -I -O -B"
2018-11-12 09:27:33 +01:00
blif
Add "whitebox" attribute, add "read_verilog -wb"
2019-04-18 17:45:47 +02:00
btor
Change "ne" to "neq" in btor2 output
2019-04-19 21:17:12 +02:00
edif
Add "whitebox" attribute, add "read_verilog -wb"
2019-04-18 17:45:47 +02:00
firrtl
Refine memory support to deal with general Verilog memory definitions.
2019-04-01 15:02:12 -07:00
ilang
Fix a syntax bug in ilang backend related to process case statements
2019-03-14 17:50:20 +01:00
intersynth
Add "whitebox" attribute, add "read_verilog -wb"
2019-04-18 17:45:47 +02:00
json
Revert "write_json to not write contents (cells/wires) of whiteboxes"
2019-04-18 23:05:59 -07:00
protobuf
Reduce amount of trailing whitespace in code base
2019-02-28 14:58:11 -08:00
simplec
Fix typographical and grammatical errors and inconsistencies.
2019-01-02 13:12:17 +00:00
smt2
Add "whitebox" attribute, add "read_verilog -wb"
2019-04-18 17:45:47 +02:00
smv
Add "whitebox" attribute, add "read_verilog -wb"
2019-04-18 17:45:47 +02:00
spice
Add "whitebox" attribute, add "read_verilog -wb"
2019-04-18 17:45:47 +02:00
table
Add "whitebox" attribute, add "read_verilog -wb"
2019-04-18 17:45:47 +02:00
verilog
Rename T_{RISE,FALL}_AVG to T_{RISE,FALL}_TYP to better match verilog std nomenclature
2019-04-23 21:36:59 +02:00