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luke
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yosys
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646ff6d32dd15f01e45f5a778b8cc2fc45b588b3
yosys
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techlibs
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quicklogic
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common
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N. Engelhardt
98769010af
synth_quicklogic: rearrange files to prepare for adding more architectures
2023-12-04 15:52:02 +01:00
..
cells_sim.v
synth_quicklogic: rearrange files to prepare for adding more architectures
2023-12-04 15:52:02 +01:00