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KrystalDelusionandKrystalDelusion
b9b5899cce
* Copies guidelines files into docs/ for website * Copying manual/CHAPTER_Prog for new docs * Copying manual/APPNOTE_011... for new docs Also adding faketime to list of packages for website build. Co-authored-by: KrystalDelusion <[email protected]>
7 lines
157 B
Verilog
7 lines
157 B
Verilog
module example(input clk, a, b, c,
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output reg [1:0] y);
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always @(posedge clk)
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if (c)
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y <= c ? a + b : 2'd0;
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endmodule
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