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mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-06 20:12:09 +02:00
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63dfbb18cfb34d72746565a3eb3ffbcd7451cdab
yosys/frontends/verilog
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History
Clifford Wolf 7188542155 Fixed clang -Wdeprecated-register warnings
2014-04-20 14:28:23 +02:00
..
.gitignore
added .gitignore files
2013-01-05 11:19:11 +01:00
const2ast.cc
Fixed handling of unsized constants in verilog frontend
2014-01-24 15:05:24 +01:00
lexer.l
Fixed clang -Wdeprecated-register warnings
2014-04-20 14:28:23 +02:00
Makefile.inc
Various improvements in support for generate statements
2013-12-04 21:06:54 +01:00
parser.y
Replaced depricated %name-prefix= bison directive
2014-04-20 14:22:11 +02:00
preproc.cc
Added Verilog support for "`default_nettype none"
2014-02-17 14:28:52 +01:00
verilog_frontend.cc
Merged OSX fixes from Siesh1oo with some modifications
2014-03-13 12:48:10 +01:00
verilog_frontend.h
Added Verilog support for "`default_nettype none"
2014-02-17 14:28:52 +01:00
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