yosys/techlibs/xilinx
Eddie Hung 6008bb7002 Revert "synth_* with -retime option now calls abc with -D 1 as well"
This reverts commit 9a6da9a79a.
2019-04-18 07:59:16 -07:00
..
tests
.gitignore
Makefile.inc Changes required for VPR place and route synth_xilinx. 2019-03-01 12:02:27 -08:00
arith_map.v Changes required for VPR place and route synth_xilinx. 2019-03-01 12:02:27 -08:00
brams.txt
brams_bb.v
brams_init.py Squelch trailing whitespace, including meta-whitespace 2018-03-11 16:03:41 +01:00
brams_map.v Revert BRAM WRITE_MODE changes. 2019-03-04 09:22:22 -08:00
cells_map.v Changes required for VPR place and route synth_xilinx. 2019-03-01 12:02:27 -08:00
cells_sim.v Remove BUFGCTRL, BUFHCE and LUT6_2 from cells_xtra. 2019-04-12 09:35:15 -07:00
cells_xtra.sh Remove BUFGCTRL, BUFHCE and LUT6_2 from cells_xtra. 2019-04-12 09:35:15 -07:00
cells_xtra.v Remove BUFGCTRL, BUFHCE and LUT6_2 from cells_xtra. 2019-04-12 09:35:15 -07:00
drams.txt
drams_map.v
ff_map.v Retry 2019-04-05 15:31:54 -07:00
lut_map.v Changes required for VPR place and route synth_xilinx. 2019-03-01 12:02:27 -08:00
synth_xilinx.cc Revert "synth_* with -retime option now calls abc with -D 1 as well" 2019-04-18 07:59:16 -07:00