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mirror of https://github.com/YosysHQ/yosys.git synced 2026-08-31 18:24:48 +02:00
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62b89bb0d4a33cd67bbc2e6463977bb007c8d414
yosys/tests/arch
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History
Lofty 9f7a55c99f intel_alm: M10K write-enable is negative-true
2022-03-09 20:18:06 +00:00
..
anlogic
anlogic: support BRAM mapping
2021-12-17 20:28:22 +08:00
common
Allow initial blocks to be disabled during tests
2021-11-13 21:53:25 +01:00
ecp5
abc9: replace cell type/parameters if derived type already processed (#2991)
2021-09-09 10:05:55 -07:00
efinix
tests: Centralize test collection and Makefile generation
2020-09-21 15:07:02 +02:00
gatemate
Add gitignore for gatemate
2021-12-03 09:56:37 +01:00
gowin
gowin: Fix LUT RAM inference, add more models.
2022-02-09 09:04:34 +01:00
ice40
test/arch/{ecp5,ice40}/memories.ys: Use read_verilog -defer.
2021-08-11 14:52:38 +02:00
intel_alm
intel_alm: M10K write-enable is negative-true
2022-03-09 20:18:06 +00:00
machxo2
iopadmap: Add native support for negative-polarity output enable.
2021-11-09 15:40:16 +01:00
nexus
memory_bram: Reuse extract_rdff helper for make_outreg.
2021-05-25 22:42:03 +02:00
quicklogic
quicklogic: ABC9 synthesis
2021-04-17 20:54:58 +02:00
xilinx
Fix the tests we just broke
2021-12-10 00:22:37 +01:00
run-test.sh
Add default assignments to SB_LUT4
2021-04-20 12:46:21 +02:00
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