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mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-01 10:39:10 +02:00
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62b89bb0d4a33cd67bbc2e6463977bb007c8d414
yosys/techlibs/gowin
T
History
YRabbit 19b7633aca gowin: add support for Double Data Rate primitives
Signed-off-by: YRabbit <[email protected]>
2022-03-14 23:14:21 +01:00
..
.gitignore
gowin: Add missing .gitignore entries
2019-11-22 14:40:36 +01:00
arith_map.v
Use HTTPS for website links, gatecat email
2021-06-09 12:16:56 +02:00
brams_init3.vh
GoWin enablement: DRAM, initial BRAM, DRAM init, DRAM sim and synth_gowin flow
2019-04-12 23:40:02 -05:00
brams_init.py
support bram initialisation
2019-09-05 17:25:51 +02:00
brams_map.v
add 32-bit BRAM and byte-enables
2019-10-28 10:33:27 +01:00
brams.txt
Harmonize BRAM/LUTRAM descriptions across all of Yosys.
2020-01-01 12:30:00 +00:00
cells_map.v
iopadmap: Add native support for negative-polarity output enable.
2021-11-09 15:40:16 +01:00
cells_sim.v
gowin: add support for Double Data Rate primitives
2022-03-14 23:14:21 +01:00
lutrams_map.v
gowin: Fix LUT RAM inference, add more models.
2022-02-09 09:04:34 +01:00
lutrams.txt
Harmonize BRAM/LUTRAM descriptions across all of Yosys.
2020-01-01 12:30:00 +00:00
Makefile.inc
gowin: replace determine_init with setundef
2020-07-04 23:26:56 +02:00
synth_gowin.cc
iopadmap: Add native support for negative-polarity output enable.
2021-11-09 15:40:16 +01:00
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