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mirror of https://github.com/YosysHQ/yosys.git synced 2026-08-31 10:15:10 +02:00
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62b89bb0d4a33cd67bbc2e6463977bb007c8d414
yosys/techlibs/anlogic
T
History
Miodrag Milanovic 36482680d5 Removed dbits 8 since 9 will always be picked
2022-01-19 08:51:25 +01:00
..
.gitignore
anlogic: support BRAM mapping
2021-12-17 20:28:22 +08:00
anlogic_eqn.cc
Fixing old e-mail addresses and deadnames
2021-06-08 00:39:36 +02:00
anlogic_fixcarry.cc
Fixing old e-mail addresses and deadnames
2021-06-08 00:39:36 +02:00
arith_map.v
Fixing old e-mail addresses and deadnames
2021-06-08 00:39:36 +02:00
brams_init.py
anlogic: support BRAM mapping
2021-12-17 20:28:22 +08:00
brams_map.v
anlogic: support BRAM mapping
2021-12-17 20:28:22 +08:00
brams.txt
Removed dbits 8 since 9 will always be picked
2022-01-19 08:51:25 +01:00
cells_map.v
anlogic: Fix FF mapping.
2020-07-17 14:03:21 +02:00
cells_sim.v
anlogic: Use dfflegalize.
2020-07-14 05:02:50 +02:00
eagle_bb.v
Revert "Leave only real black box cells"
2018-12-17 23:20:40 +08:00
lutram_init_16x4.vh
Harmonize BRAM/LUTRAM descriptions across all of Yosys.
2020-01-01 12:30:00 +00:00
lutrams_map.v
Harmonize BRAM/LUTRAM descriptions across all of Yosys.
2020-01-01 12:30:00 +00:00
lutrams.txt
Harmonize BRAM/LUTRAM descriptions across all of Yosys.
2020-01-01 12:30:00 +00:00
Makefile.inc
anlogic: support BRAM mapping
2021-12-17 20:28:22 +08:00
synth_anlogic.cc
anlogic: support BRAM mapping
2021-12-17 20:28:22 +08:00
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