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mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-04 03:23:11 +02:00
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60fb9cabcfad985a4f35acaa74fd6e63b45081bc
yosys/techlibs
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Xark 9509444ef2 Fix Verilator sim warnings: 1 BLKSEQ and 3 WIDTH
2020-06-14 00:45:22 -07:00
..
achronix
Add force_downto and force_upto wire attributes.
2020-05-19 01:42:40 +02:00
anlogic
Add force_downto and force_upto wire attributes.
2020-05-19 01:42:40 +02:00
common
Do not optimize away FFs in "prep" and Verific fron-end
2020-06-09 15:54:14 +02:00
coolrunner2
Add force_downto and force_upto wire attributes.
2020-05-19 01:42:40 +02:00
easic
Update doc that "-retime" calls abc with "-dff -D 1"
2019-12-30 13:28:29 -08:00
ecp5
ecp5: cleanup unused +/ecp5/abc9_model.v
2020-05-23 08:17:40 -07:00
efinix
Add force_downto and force_upto wire attributes.
2020-05-19 01:42:40 +02:00
gowin
Add force_downto and force_upto wire attributes.
2020-05-19 01:42:40 +02:00
greenpak4
Add force_downto and force_upto wire attributes.
2020-05-19 01:42:40 +02:00
ice40
Fix Verilator sim warnings: 1 BLKSEQ and 3 WIDTH
2020-06-14 00:45:22 -07:00
intel
Add force_downto and force_upto wire attributes.
2020-05-19 01:42:40 +02:00
intel_alm
intel_alm: fix DFFE matching
2020-06-11 19:55:51 +02:00
sf2
Add force_downto and force_upto wire attributes.
2020-05-19 01:42:40 +02:00
xilinx
xilinx: tidy up cells_sim.v a little
2020-05-25 09:48:11 -07:00
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